The performance of digital systems is heavily dependent on the frequency. On the other hand, the higher the frequency, the shorter is the time remaining to convey digital signals reliably from a driver via a conductor track to the receivers. Limiting factors are the clock-to-output time (tco), the run time on the board (trun), the setup/hold time (tsetup/thold) of the receiver, output and input skew (skew of the transmitters and receivers) and clock skew or jitter (tskew).
FIG. 1 shows the timing of a digital signal at the output of the driver of a transmitter and at the input of the receiver, the diagram illustrating the time effect of the factors mentioned.
The setup time requirement determines for how many ns before the clock edge a signal to be clocked in has to be stable. The hold time requirement determines for how long after a clock edge the signal has to remain stable. Thus, if the position of the times of clock and signal with respect to each other is varied, this has a positive effect in respect of one requirement, but a negative effect in respect of the other requirement. The run time of clock and signals must be optimized in such a way that even in extreme environmental conditions positive margins remain and no timing violations arise anywhere. The tradeoff determines the maximum possible frequency and therefore the performance of the system or imposes constraints in the architecture.
With bidirectional signals, the optimization is even more difficult. If, for example, a relatively large run time arises in any case due to a great distance between transmitter and receiver, complying with the hold time is no problem.
On the other hand this probably gives rise to a problem with regard to the setup time. With unidirectional signals a means of optimizing could be to allow the clock of the receivers to trail behind somewhat relative to the clock of the transmitter. In this way more time is gained for setup and the amply available hold time is reduced. The clock period is lengthened somewhat for this direction.
With bidirectional signals this is impossible. In the opposite direction the receiver clock would then in fact be leading the transmitter clock. The clock period would be shortened. Moreover this would happen in spite of the fact that the distance for the signals is actually the same. Each change in favor of one direction is detrimental to the timing of the other direction.
For simple digital circuits, no solution at all was found for this problem. Generally measures are taken to ensure that the two transmitters/receivers involved have as little clock skew as possible. In this way the timing budget for both direction is the same. An optimization in favor of one direction was possible only if the two devices differed in the setup/hold or clock-to-output values according to the data sheet.
Typically, a table is produced which lists all the timing parameters to be taken into account for each signal and for both directions and calculates a margin or a violation.
TABLE 1Setup and hold time margin calculation (for one direction;another table for reverse direction)signaltskewtco,tco,trun,trun,holdsetupnamechipminmaxminmaxtsetuptholdmarginmar-ginhold margin = tco, min + trun, min − tskew − tholdsetup margin = 7.5 ns − tco, max − trun, max − tsetup − tskew(clock period = 7.5 ns)
In special digital systems (e.g. RAMBUS or DDR SDRAM), measures are taken to ensure that the signals are not clocked in using the centrally distributed clock, but are clocked in with a delay by means of the clock signals also supplied, which are known as strobe signals. This presupposes that the devices involved also supply these strobe signals. Simpler circuits do not have this possibility.
An already partly common variant for minimizing the clock skew between transmitter and receiver, which is shown in FIG. 2, uses a PLL in the transmitter device (e.g. SDRAM controller). In this arrangement, clock and signals for the SDRAMs come from the same chip. An additional clock output is looped back again to the PLL of the transmitter and in fact has the same physical length as the SDRAM clocks. The PLL transmits this feedback clock earlier in line with the board run time, so that in this way it will then arrive in phase with the reference clock at the PLL input of the SDRAM controller. Because the clocks have the same run time to the SDRAM these are also automatically in phase at their receivers.